"Early timing estimation for system-level design using FPGAs (abstract only)."

Hugo A. Andrade et al. (2012)

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DOI: 10.1145/2145694.2145761

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - https://dblp.org/rec/conf/fpga/AndradeGLMPRTWY12
Hugo A. Andrade, Arkadeb Ghosal, Rhishikesh Limaye, Sadia Malik, Newton Petersen, Kaushik Ravindran, Trung N. Tran, Guoqiang Wang, Guang Yang:
Early timing estimation for system-level design using FPGAs (abstract only). FPGA 2012: 271

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