"FPGA power reduction by guarded evaluation."

Jason Helge Anderson, Chirag Ravishankar (2010)

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DOI: 10.1145/1723112.1723141

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Jason Helge Anderson, Chirag Ravishankar:
FPGA power reduction by guarded evaluation. FPGA 2010: 157-166

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