"Estimating worst-case latency of on-chip interconnects with formal simulation."

Freek Verbeek, Nike van Vugt (2017)

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DOI: 10.23919/FMCAD.2017.8102261

access: closed

type: Conference or Workshop Paper

metadata version: 2017-11-17

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Freek Verbeek, Nike van Vugt:
Estimating worst-case latency of on-chip interconnects with formal simulation. FMCAD 2017: 204-211

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