"Design Validation of Recurrent Signal Processor FPGA prototype."

Yury Stepchenkov et al. (2021)

> Home

Details and statistics

DOI: 10.1109/EWDTS52692.2021.9581005

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ewdts/StepchenkovKSO21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ewdts/StepchenkovKSO21
Yury Stepchenkov, Dmitry Khilko, Yury Shikunov, Georgy Orlov:
Design Validation of Recurrent Signal Processor FPGA prototype. EWDTS 2021: 1-5

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.