"Logic Synthesis and Verification of the CPU and Caches of a Mainframe System."

Huy Nam Nguyen et al. (1994)

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DOI: 10.1109/EDTC.1994.326898

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet:
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System. EDAC-ETC-EUROASIC 1994: 60-64

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