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"Circuit and process co-design with vertical gate-all-around nanowire FET ..."

Trong Huynh Bao et al. (2014)

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DOI: 10.1109/ESSDERC.2014.6948768

access: closed

type: Conference or Workshop Paper

metadata version: 2019-05-24

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  - conf/essderc/BaoYRCBVBCRDRMTVTW14
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  - https://dblp.org/rec/conf/essderc/BaoYRCBVBCRDRMTVTW14
Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq:
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC 2014: 102-105

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