"Design margin elimination in a near-threshold timing error masking-aware ..."

Hans Reyserhove, Wim Dehaene (2017)

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DOI: 10.1109/ESSCIRC.2017.8094549

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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Hans Reyserhove, Wim Dehaene:
Design margin elimination in a near-threshold timing error masking-aware 32-bit ARM Cortex M0 in 40nm CMOS. ESSCIRC 2017: 155-158

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