"Designing energy efficient and hysteresis free negative capacitance FinFET ..."

Girish Pahwa et al. (2016)

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DOI: 10.1109/ESSCIRC.2016.7598240

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

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Girish Pahwa, Tapas Dutta, Amit Agarwal, Yogesh Singh Chauhan:
Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach. ESSCIRC 2016: 49-54

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