"Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits."

Christian Pacha et al. (2007)

> Home

Details and statistics

DOI: 10.1109/ESSCIRC.2007.4430258

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-18

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/esscirc/PachaABSXSMBCSB07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/esscirc/PachaABSXSMBCSB07
Christian Pacha, Klaus von Arnim, Florian Bauer, Thomas Schulz, Wade Xiong, K. T. San, Andrew Marshall, Thomas Baumann, C. Rinn Cleavelin, Klaus Schruefer, Jörg Berthold:
Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits. ESSCIRC 2007: 111-114

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.