"A 128-bit chip identification generating scheme exploiting SRAM bitcells ..."

Shunsuke Okumura et al. (2011)

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DOI: 10.1109/ESSCIRC.2011.6044938

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-11

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Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10^-19. ESSCIRC 2011: 527-530

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