"An 11.75-Gb/s combined decision feedback equalizer and clock data recovery ..."

Lijun Li, Michael M. Green (2007)

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DOI: 10.1109/ESSCIRC.2007.4430353

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-18

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Lijun Li, Michael M. Green:
An 11.75-Gb/s combined decision feedback equalizer and clock data recovery circuit in 0.18-μm CMOS. ESSCIRC 2007: 508-511

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