"A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS."

Hao Li et al. (2018)

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DOI: 10.1109/ESSCIRC.2018.8494285

access: closed

type: Conference or Workshop Paper

metadata version: 2021-12-21

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Hao Li, Ganesh Balamurugan, James E. Jaussi, Bryan Casper:
A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS. ESSCIRC 2018: 238-241

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