"A low-noise, 8.95-11GHz all-digital frequency synthesizer with a ..."

Chen Jiang et al. (2012)

> Home

Details and statistics

DOI: 10.1109/ESSCIRC.2012.6341330

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/esscirc/JiangLHH12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/esscirc/JiangLHH12
Chen Jiang, Junren Liu, Yumei Huang, Zhiliang Hong:
A low-noise, 8.95-11GHz all-digital frequency synthesizer with a metastability-free time-to-digital converter and a sleepy counter in 65nm CMOS. ESSCIRC 2012: 365-368

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.