"A power cut-off technique for gate leakage suppression [CMOS logic circuits]."

Mindaugas Draidiiulis et al. (2004)

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DOI: 10.1109/ESSCIR.2004.1356645

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-29

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Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson:
A power cut-off technique for gate leakage suppression [CMOS logic circuits]. ESSCIRC 2004: 171-174

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