"Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI ..."

Vivek Asthana et al. (2013)

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DOI: 10.1109/ESSCIRC.2013.6649161

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-23

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Vivek Asthana, Malathi Kar, Jean Jimenez, Jean-Philippe Noel, Sébastien Haendler, Philippe Galy:
Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control. ESSCIRC 2013: 415-418

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