"Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel ..."

Yuto Miura et al. (2024)

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DOI: 10.1109/ICEIC61013.2024.10457150

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-02

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Yuto Miura, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits. ICEIC 2024: 1-2

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