"Speed-Area-Power Efficient Ternary Logic Gate Implementation Based on ..."

Gihyeon Jeon, Daejin Park (2024)

> Home

Details and statistics

DOI: 10.1109/ICEIC61013.2024.10457139

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/elinfocom/JeonP24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/elinfocom/JeonP24
Gihyeon Jeon, Daejin Park:
Speed-Area-Power Efficient Ternary Logic Gate Implementation Based on Typical MOS Transistors. ICEIC 2024: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.