![](https://dblp.uni-trier.de./img/logo.320x120.png)
![search dblp search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
default search action
"Design of Memory Access Module for YOLO v2 Neural Network Accelerator ..."
Jun Li et al. (2020)
- Jun Li, Ying Liang, Shengkai Wang, Jun Yang:
Design of Memory Access Module for YOLO v2 Neural Network Accelerator Based on FPGA. EITCE 2020: 658-662
![](https://dblp.uni-trier.de./img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.