"Design-space exploration of ultra-low power CMOS logic gates in a 28 nm ..."

Marten Vohrmann et al. (2017)

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DOI: 10.1109/ECCTD.2017.8093232

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-26

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  - https://dblp.org/rec/conf/ecctd/VohrmannGJ017
Marten Vohrmann, Philippe Geisler, Thorsten Jungeblut, Ulrich Rückert:
Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. ECCTD 2017: 1-4

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