"TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error ..."

Raghunandana K. K et al. (2024)

> Home

Details and statistics

DOI: 10.1109/DDECS60919.2024.10508915

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ddecs/KRRS24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ddecs/KRRS24
Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh:
TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. DDECS 2024: 104-109

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.