"An architecture and an FPGA prototype of a reliable processor pipeline ..."

Abdelmajid Bouajila et al. (2011)

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DOI: 10.1109/DDECS.2011.5783084

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf:
An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. DDECS 2011: 225-230

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