"Benchmarking Large Language Models for Automated Verilog RTL Code Generation."

Shailja Thakur et al. (2023)

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DOI: 10.23919/DATE56975.2023.10137086

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type: Conference or Workshop Paper

metadata version: 2023-11-12

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Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan, Ramesh Karri, Brendan Dolan-Gavitt, Siddharth Garg:
Benchmarking Large Language Models for Automated Verilog RTL Code Generation. DATE 2023: 1-6

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