"A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact ..."

Hisashi Sasaki (1999)

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DOI: 10.1109/DATE.1999.761145

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Hisashi Sasaki:
A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine. DATE 1999: 353-

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