"Formal verification of analog circuits in the presence of noise and ..."

Rajeev Narayanan et al. (2010)

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DOI: 10.1109/DATE.2010.5457009

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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  - https://dblp.org/rec/conf/date/NarayananAZTP10
Rajeev Narayanan, Behzad Akbarpour, Mohamed H. Zaki, Sofiène Tahar, Lawrence C. Paulson:
Formal verification of analog circuits in the presence of noise and process variation. DATE 2010: 1309-1312

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