"FPGA latency optimization using system-level transformations and DFG ..."

Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier (2013)

> Home

Details and statistics

DOI: 10.7873/DATE.2013.316

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

- view
  authority control:
- export record
  dblp key:
  - conf/date/Gomez-PradoCT13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/date/Gomez-PradoCT13
Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier:
FPGA latency optimization using system-level transformations and DFG restructuring. DATE 2013: 1553-1558

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.