"Enabling concurrent clock and power gating in an industrial design flow."

Letícia Maria Veiras Bolzani et al. (2009)

> Home

Details and statistics

DOI: 10.1109/DATE.2009.5090684

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

- view
  authority control:
- export record
  dblp key:
  - conf/date/BolzaniCMMP09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/date/BolzaniCMMP09
Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Enabling concurrent clock and power gating in an industrial design flow. DATE 2009: 334-339

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.