"Timing Optimization on Mapped Circuits."

Ko Yoshikawa et al. (1991)

> Home

Details and statistics

DOI: 10.1145/127601.127639

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/dac/YoshikawaITSNK91
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dac/YoshikawaITSNK91
Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh:
Timing Optimization on Mapped Circuits. DAC 1991: 112-117

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.