"Area-optimized low-latency approximate multipliers for FPGA-based hardware ..."

Salim Ullah et al. (2018)

> Home

Details and statistics

DOI: 10.1145/3195970.3195996

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-04

- view
  authority control:
- export record
  dblp key:
  - conf/dac/UllahRPKH0018
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dac/UllahRPKH0018
Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, Akash Kumar:
Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators. DAC 2018: 159:1-159:6

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.