"MIXS: A mixed level simulator for large digital system logic verification."

Tohru Sasaki et al. (1980)

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DOI: 10.1145/800139.804596

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu:
MIXS: A mixed level simulator for large digital system logic verification. DAC 1980: 626-633

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