"Built-In Test Sequence Generation for Synchronous Sequential Circuits ..."

Irith Pomeranz, Sudhakar M. Reddy (1999)

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DOI: 10.1145/309847.310052

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Irith Pomeranz, Sudhakar M. Reddy:
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. DAC 1999: 754-759

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