"Combine and top down block placement algorithm for hierarchical logic VLSI ..."

Tokinori Kozawa, Chihei Miura, Hidekazu Terai (1984)

> Home

Details and statistics

DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2012-03-01

- view
  - electronic edition @ acm.org
- export record
  dblp key:
  - conf/dac/KozawaMT84
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dac/KozawaMT84
Tokinori Kozawa, Chihei Miura, Hidekazu Terai:
Combine and top down block placement algorithm for hierarchical logic VLSI layout. DAC 1984: 667-669

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.