"A delay test system for high speed logic LSI's."

Kuniaki Kishida et al. (1986)

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DOI: 10.1145/318013.318161

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Kuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi:
A delay test system for high speed logic LSI's. DAC 1986: 786-790

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