"Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA."

Roberto Ramírez Marín et al. (2005)

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DOI: 10.1109/CONIEL.2005.44

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/conielecomp/MarinGPV05
Roberto Ramírez Marín, Andrés David García García, Luis Fernando González Pérez, Javier Eduardo González Villarruel:
Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA. CONIELECOMP 2005: 70-75

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