"High-level synthesis for large bit-width multipliers on FPGAs: a case study."

Gang Quan et al. (2005)

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DOI: 10.1145/1084834.1084890

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell:
High-level synthesis for large bit-width multipliers on FPGAs: a case study. CODES+ISSS 2005: 213-218

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