"A modular simulation framework for architectural exploration of on-chip ..."

Tim Kogel et al. (2003)

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DOI: 10.1145/944645.944648

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/codes/KogelDWLAMG03
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  - https://dblp.org/rec/conf/codes/KogelDWLAMG03
Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens:
A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS 2003: 7-12

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