"Gate stack resistance and limits to CMOS logic performance."

Richard A. Wachnik et al. (2013)

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DOI: 10.1109/CICC.2013.6658494

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Richard A. Wachnik, Sungjae Lee, Li-Hong Pan, Ning Lu, Hongmei Li, Raphael Bingert, Mai Randall, Scott K. Springer, Christopher S. Putnam:
Gate stack resistance and limits to CMOS logic performance. CICC 2013: 1-4

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