"A single-chip low power DSP/RISC CPU with 0.25 μm CMOS technology."

Takashi Shikata et al. (1998)

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DOI: 10.1109/CICC.1998.694920

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-11

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Takashi Shikata, Shinya Kondou, Masanori Nose, Yoshio Kuniyasu, Mutsuhiro Naitoh, Hidetaka Suzuki:
A single-chip low power DSP/RISC CPU with 0.25 μm CMOS technology. CICC 1998: 123-126

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