"A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for ..."

Dirk Pfaff et al. (2019)

> Home

Details and statistics

DOI: 10.1109/CICC.2019.8780247

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/cicc/PfaffAWZMSL19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/cicc/PfaffAWZMSL19
Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin:
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET. CICC 2019: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.