"A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os."

Hiok-Tiaq Ng et al. (2003)

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DOI: 10.1109/CICC.2003.1249363

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-08

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Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran:
A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. CICC 2003: 77-80

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