"Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity ..."

Daisuke Kosaka et al. (2007)

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DOI: 10.1109/CICC.2007.4405861

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-30

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Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata:
Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation. CICC 2007: 849-852

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