"Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using ..."

Walter Fergusson, Rakesh H. Patel, William Bereza (2007)

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DOI: 10.1109/CICC.2007.4405863

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Walter Fergusson, Rakesh H. Patel, William Bereza:
Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A. CICC 2007: 857-860

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