"A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a ..."

Simone Mattia Dartizio et al. (2024)

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DOI: 10.1109/CICC60959.2024.10529002

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type: Conference or Workshop Paper

metadata version: 2024-10-06

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Simone Mattia Dartizio, Michele Rossoni, Francesco Tesolin, Giacomo Castoro, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector. CICC 2024: 1-2

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