![](https://dblp.uni-trier.de./img/logo.320x120.png)
![search dblp search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
default search action
"Performance optimization in flip flop circuit design."
Himadri Nath Saha et al. (2018)
- Himadri Nath Saha, Pooja Joshi, Adriza Chattopadhyay, Barsha Deb, Anurupa Ghosh, Puja Kumari, Dipak Kumar Mahato, Sayantani Choudhuri, Sayani Bhattacharjee, Sourav Chattopadhyay, Pranami Dash, Basab BijoyGharai:
Performance optimization in flip flop circuit design. CCWC 2018: 421-423
![](https://dblp.uni-trier.de./img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.