"Hardware Design and Verification Techniques for Supply Chain Risk Mitigation."

Bao Liu, Yier Jin, Gang Qu (2015)

> Home

Details and statistics

DOI: 10.1109/CADGRAPHICS.2015.53

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/cadgraphics/LiuJQ15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/cadgraphics/LiuJQ15
Bao Liu, Yier Jin, Gang Qu:
Hardware Design and Verification Techniques for Supply Chain Risk Mitigation. CAD/Graphics 2015: 238-239

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.