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"An approach to synthesis delay semantics in VHDL."

Lixin Cheng, Jinian Bian, Yunyun Liu (2009)

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DOI: 10.1109/CADCG.2009.5246855

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  dblp key:
  - conf/cadgraphics/ChengBL09
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  - https://dblp.org/rec/conf/cadgraphics/ChengBL09
Lixin Cheng, Jinian Bian, Yunyun Liu:
An approach to synthesis delay semantics in VHDL. CAD/Graphics 2009: 492-496

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