"Design of a Switch-Level Analog Model for Verilog."

Thomas J. Sheffler (2008)

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DOI: 10.1109/BMAS.2008.4751252

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Thomas J. Sheffler:
Design of a Switch-Level Analog Model for Verilog. BMAS 2008: 118-123

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