"Single-Chip 30 GHz SiGe Sub-Sampling PLL with 28.3 fs Jitter."

Dimitre Dimitrov et al. (2024)

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DOI: 10.1109/BCICTS59662.2024.10745698

access: closed

type: Conference or Workshop Paper

metadata version: 2024-11-28

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Dimitre Dimitrov, Mark D. Hickle, Matthew Speir, Joseph M. Krzyzek, Daniel P. Lacroix, Shail Srinivas, Robert Sepanek, Spencer Desrochers, Steven Eugene Turner:
Single-Chip 30 GHz SiGe Sub-Sampling PLL with 28.3 fs Jitter. BCICTS 2024: 266-269

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