"A Temporal Assertion Extension to Verilog."

Kai-Hui Chang et al. (2004)

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DOI: 10.1007/978-3-540-30476-0_45

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo:
A Temporal Assertion Extension to Verilog. ATVA 2004: 499-504

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