"Yield, Overall Test Environment Timing Accuracy, and Defect Level ..."

Baosheng Wang et al. (2003)

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DOI: 10.1109/ATS.2003.1250835

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov:
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. Asian Test Symposium 2003: 348-353

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