"A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital ..."

D. A. Tran et al. (2011)

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DOI: 10.1109/ATS.2011.89

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141

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